The semiconductor industry makes wide use of standard BGA (ball grid array) type semiconductor packages. Such packages generally include a BT (bismaleimide triazine) core having various metallization and solder mask layers to form the substrate. A semiconductor die is attached to the substrate and electrically connected to various electrical connections of the substrate using ball attach or wire-bonding techniques. The wire bonds and the die are typically encapsulated with a protective layer of encapsulant. Such packages and the methods of their construction are well known to persons having ordinary skill in the semiconductor packaging arts. Additionally, ball attach arrangements are provided with an underfill encapsulant to protect the bonding arrangements of the solder balls.
Commonly, the packages are then provided with a stiffener and a heat spreader to complete the packages. These completed packages are then subject to a series of tests used to qualify the packages to insure they meet all the necessary specifications prior to shipping.
One such test subjects the package to a series of electrostatic discharge (ESD) events to determine the packages robustness and resistance to these ESD events. In the present art, each of the ball pins of a ball grid array type package are tested for charge coupled electrostatic discharge failures. To alleviate this problem each die includes shunt circuitry associated with each external connection. One purpose of this shunt circuitry is to provide a level of resistance to ESD events.
Commonly, testing is done using a device specifically constructed for administering such testing. One example of such a tester is an Orion CDM Tester produced by Oryx Instruments Corporation of Fremont, Calif. Such equipment can be programmed to implement testing for compliance in accordance with a number of test standards. Typical examples being provided by the JEDEC, AEC, and ESDA standards as well as others. One particular standard being JEDEC No. JESD22-C101C.
FIG. 1 is a simplified schematic cross-section view of a portion of a standard PBGA (plastic ball grid array) package 101 arranged on a tester. Commonly, such packages 101 include a substrate 102 or core. The core is typically sandwiched between two metallization layers which also include layers of solder mask. Most commonly, the core 102 is formed of fiber material suspended in a cured a BT resin material. This core 102 is then treated to form metallization layers. Commonly, copper materials or coated copper materials are used. Other conductive materials are also used. A solder mask layer is then formed over the metallization layers. Typically, the solder mask layer is photolithographically patterned to create a solder mask that can be used to define a corresponding pattern in the metallization layers. Such substrates are commonly very thin, for example, less than about 0.60 mm thick. The methods of accomplishing this are very well known to those having ordinary skill in the art
With continued reference to FIG. 1, the substrate 102 forms part of a semiconductor package 101. Ball attach pads are typically formed on a backside 105 surface of the substrate 102. Solder balls 115 are typically formed on the ball attach pads. Additionally, a semiconductor integrated circuit die 110 is mounted to the front side 106 surface of the substrate 102. In many implementations, solder balls electrically connect the die 110 to associated electrical contact points on the substrate 101. Vias (not shown in this simplified view) formed in and through the substrate 102 enable the electrical communication between circuitry of the die 110 and the solder balls 115 mounted on the backside 105 of the package 101. The die and electrical connections at the interface between the die 110 and substrate 102 are commonly encapsulated in a protective layer 112 of encapsulating underfill material.
Additionally, many prior art devices include a metal stiffener 103 and a heat spreaders 104. Such elements are known to persons having ordinary skill in the art.
With continued reference to FIG. 1, the package 101 is typically placed upside down (solder ball side up) on a tester 120. As shown here, the package is placed on an insulated tester board for testing. For example, the package 101 is placed on a tester chuck 12 which has a layer of insulating material 122 (e.g., FR-4 or other such materials). The tester board (121, 122) is set at some predetermined electrical potential (e.g., 500 volts). Then a testing probe 123 descends to contact each of solder balls of the package 101. The probe is commonly set at ground. If the package survives pre-selected test routine without damage the packaged is “qualified”.
This commonly constructed package has provided satisfactory ESD protection until recently. Now, with increasing scaling of circuit elements formed on the die, smaller less ESD resistant devices and elements are becoming more common. These devices have increased vulnerability to ESD events. Thus, the traditional package format is increasingly lacking in the ability to protect these vulnerable elements from ESD events. Accordingly, the incidence of ESD induced package failure has been rising and is expected to continue to do so as circuitry and device sizes continue to shrink.
Accordingly, what is needed is a packaging design and approach that provides increased resistance to ESD induced package failure.